People who talk about ASIC have no clue how difficult and expensive it's become. Sadly, the days of 130-micron cheap fabs are behind us and designs need to work sub 90-nanometre. If you don't have a million dollars to spare and aren't targeting 100K volume or better, do NOT waste your time thinking about it.
That absurdity aside, putting each
Amiga chip (Agnus/Denise/Palua) into an FPGA would not be very hard, and in-fact, most of the MiniMig files seem to keep each chip logic fairly separate. The whole chipset fit into a single 400,000 gate Spartan, so we're not talking about big chips here -- around 150,000 gates each?
Which is still absurdly huge -- the original ECS chipset was supposed to be around 27,000 gates, so we're 5 times the size with the MiniMig reimplementation. I believe when Jeri looked at the design of MiniMig she commented on all the pointless buffering and how complex it was versus the real chips. Sadly, without a real reference we'll never know.
I would recommend looking at instant-on FPGA's such as the ProASIC3 or IGLOO from Microsemi. The normal delay of programming the FPGA at power-on might take too long. There's a 5x5mm CSP with 81 IO called the IGLOO nano which might spare enough board space to pack on all the buffers for level shifting to 5V. However, even the 14x14mm VQPF packages should fit in a DIP48 form-factor and still have room for the shifters.
This FPGA's use Flash fabric instead of SRAM and aren't based on Microsemi's older 'antifuse' technology. They are every bit as fast as SRAM devices when running and have the benefit of being completely non-volatile. There are already several FPGA's on PLCC out there and some VERY tiny ProASIC3 boards on DIP boards.
This isn't pin-compatible, but shows how everything could fit.